1.波形图

2.代码段

`timescale 1ns/10ps
module hxd(
clk,
rst,
led_out
);
input clk;
input rst;
output[3:0] led_out;reg[3:0] led_out;
reg[5:0] count_1us;
reg[9:0] count_1ms;
reg[9:0] count_1s;reg   cnt_en;
parameter   count_1us_max=6'd49;
parameter   count_1ms_max=10'd999;
parameter   count_1s_max=10'd999;always@(posedge clk or negedge rst)
beginif(rst==0)count_1us<=0;else if(count_1us==count_1us_max)count_1us<=0;elsecount_1us<=count_1us+1;end always@(posedge clk or negedge rst)
beginif(rst==0)count_1ms<=0;else  if((count_1ms==count_1ms_max)&&(count_1us==count_1us_max))count_1ms<=0;else if(count_1us==count_1us_max)count_1ms<=count_1ms+1;elsecount_1ms<=count_1ms;end always@(posedge clk or negedge rst)
beginif(rst==0)count_1s<=0;else if((count_1s==count_1s_max)&&(count_1ms==count_1ms_max)&&(count_1us==count_1us_max))count_1s<=0;else if((count_1ms==count_1ms_max)&&(count_1us==count_1us_max))count_1s<=count_1s+1;elsecount_1s<=count_1s;endalways@(posedge clk or negedge rst)beginif(rst==0)cnt_en<=0;else if((count_1s==count_1s_max)&&(count_1ms==count_1ms_max)&&(count_1us==count_1us_max))cnt_en<=~cnt_en;elsecnt_en<=cnt_en;endalways@(posedge clk or negedge rst)begin if(rst==0)led_out<=1;else if(((cnt_en==0)&&(count_1ms<=count_1s))||((cnt_en==1)&&(count_1ms>=count_1s)))//重点关注led_out<=0;elseled_out<=1;
end
endmodule

 3.仿真代码

`timescale 1ns/10ps
module hxd_tb();
reg        clk;
reg        rst;
wire       led_out;hxd u0(.clk(clk),.rst(rst),.led_out(led_out)
);
initial begin
clk=0;
rst<=0;#25 rst<=1;
end
always #10 clk<=~clk;
endmodule