代码如下

//2021-11-4
//最简单的状态机，三角波发生器；
`timescale 1ns/10ps
module tri_gen(clk,res,d_out);
input		clk,res;
output[8:0]	d_out;reg			state;
reg[8:0]	d_out;always@(posedge clk or negedge res)
if(~res) beginstate<=0;d_out<=0;
end 
else begin case(state)0://上升begind_out<=d_out+1;if(d_out==299) beginstate<=1;end end 1://下降；begin d_out<=d_out-1;if(d_out==1) beginstate<=0;end endendcase
end endmodule//------testbench of tri_gen----
module tri_gen_tb;
reg			clk,res;
wire[8:0]	d_out;tri_gen U1(.clk(clk),.res(res),.d_out(d_out));initial beginclk<=0;res<=0;#17	res<=1;#20000	$stop;
end always #5	clk<=~clk;endmodule

仿真结果如下

 增加一个状态后，代码如下（注意增加state的位宽，有剩余的状态要加default）

//2021-11-4
//最简单的状态机，三角波发生器；
`timescale 1ns/10ps
module tri_gen(clk,res,d_out);
input		clk,res;
output[8:0]	d_out;reg[1:0]	state;
reg[8:0]	d_out;
reg[7:0]	con;always@(posedge clk or negedge res)
if(~res) beginstate<=0;d_out<=0;con<=0;
end 
else begin case(state)0://上升begind_out<=d_out+1;if(d_out==299) beginstate<=1;end end 1://平顶；beginif(con==200) beginstate<=2;con<=0;end else begincon<=con+1;end end 2://下降；begin d_out<=d_out-1;if(d_out==1) beginstate<=0;end enddefault://beginstate<=0;con<=0;d_out<=0;end endcase
end endmodule//------testbench of tri_gen----
module tri_gen_tb;
reg			clk,res;
wire[8:0]	d_out;tri_gen U1(.clk(clk),.res(res),.d_out(d_out));initial beginclk<=0;res<=0;#17	res<=1;#20000	$stop;
end always #5	clk<=~clk;endmodule

三状态仿真结果如下

 四状态的代码如下

//2021-11-4
//最简单的状态机，三角波发生器；
`timescale 1ns/10ps
module tri_gen(clk,res,d_out);
input		clk,res;
output[8:0]	d_out;reg[1:0]	state;
reg[8:0]	d_out;
reg[7:0]	con;always@(posedge clk or negedge res)
if(~res) beginstate<=0;d_out<=0;con<=0;
end 
else begin case(state)0://上升begind_out<=d_out+1;if(d_out==299) beginstate<=1;end end 1://平顶；beginif(con==200) beginstate<=2;con<=0;end else begincon<=con+1;end end 2://下降；begin d_out<=d_out-1;if(d_out==1) beginstate<=3;end end3://平顶；beginif(con==200) beginstate<=0;con<=0;end else begincon<=con+1;end end endcase
end endmodule//------testbench of tri_gen----
module tri_gen_tb;
reg			clk,res;
wire[8:0]	d_out;tri_gen U1(.clk(clk),.res(res),.d_out(d_out));initial beginclk<=0;res<=0;#17	res<=1;#20000	$stop;
end always #5	clk<=~clk;endmodule

四状态的仿真结果如下

https://www.bilibili.com/video/BV1hX4y137Ph?p=7&spm_id_from=pageDriver